Embodiments herein generally relate to the field of circuit design, and, more particularly, to electronic design automation (EDA) tools to perform verification of untimed nets.
In the field of integrated circuit (IC) design, digital electronic circuits are typically initially represented by a high-level abstraction written in a hardware description language (HDL). Verification, e.g., functional analysis, is performed on a model of the HDL representation, also referred to as an RTL model, to ensure it meets its functional specifications. The HDL representation allows a circuit designer to express all the desired functionality of a digital electronic circuit at the register transfer level (RTL) of abstraction. The HDL representation is then converted into a circuit file through a process known as synthesis that involves translation and optimization. Finally, static timing analysis and equivalence checking are performed on the circuit file. Static timing analysis verifies that the circuit design performs at target clock speeds. Equivalence checking ensures that the circuit file is functionally correct compared to the HDL.
Static timing analysis is used to verify that transitioning values from source latches to sink latches in the nets, or signals, of the circuit design will satisfy the timing requirements of the synchronous logic. In order to simplify static timing analysis, circuit designers commonly identify and eliminate a selected set of non-critical timing paths throughout a circuit design when performing static timing analysis on the circuit design. Such set of non-critical timing paths are usually referred to as a snip, exception, or “don't care” (DC) adjusted list or file (referred to hereafter as a DC adjusted (dcadj) list). The dcadj list may be passed to the static timing tools to thereby identify to the static timing tools that certain nets, or net segments, need not adhere to static timing requirements since their value will not transition or change. These nets are referred to herein as untimed nets or untimed signals since “signal” and “net” are used interchangeably in this application.
A problem arises, however, in that a human designer decides on the dcadj list that is provided to the static timing tool. The designer may think the dcadj list is correct, however, they may fail to realize that some nets specified as untimed nets in the dcadj list will not be “don't care” in certain modes (or conditions) of operation, and thus, should be considered when performing verification. It is also possible that the entry is in a form of a regular expression which inadvertently matches more points (nets or box/pin pairs) in the logic than intended.